sampling clock meaning in English
取样钟
Examples
- Of course the sampling clock is itself a digital signal
时钟本身也是数字信号，也会干扰模拟电路。 - The sampling clock generator must also have adequate spectral purity
时钟发生电路固有的抖动应该足够小。 - Figure 5 . 36 shows the relationship between sampling clock jitter and snr previously presented
图5 . 36显示了采样时钟抖动和信噪比之间的关系。 - To achieve this the sampling clock should be isolated as much as possible from the noise present in the digital parts of the system
为此，时钟信号应该尽可能地与电路中强噪声的部分隔离开，例如数字电路。 - The adc aperture jitter must be minimal , and the sampling clock generated from a low phase - noise quartz crystal oscillator
Adc的孔径抖动必需尽可能的小，而且要使用低相位噪声的石英晶体振荡器作为采样时钟发生器。